Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (IC's).
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.” Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.
Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.
IC layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional graphical IC layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Mentor Graphics, Inc., and the more recent Open Artwork System Interchange Standard (OASIS) proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in IC layout designs that are employed to manufacture integrated circuits. Once the microcircuit device design is finalized, the layout portion of the design can be used by fabrication tools to manufacturer the device using a photolithographic process.
There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.
Each time that a layer of material is exposed to radiation, a mask must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in layout design data define the relative locations or areas of the circuit device that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask or reticle based upon the layout design data, after which the mask can be used in a photolithographic process. A mask is traditionally created by covering selected portions of a transparent “plate” with a material that does not transmit light. The image or features created in the mask after the non-transmitting material is applied are often referred to as the intended or target images, while the image created on the substrate, by employing the mask in the photolithographic process is referred to as the printed image.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. To address this problem, various resolution enhancement techniques (RET) are often employed to improve the fidelity of the optical lithographic process. For example, optical process correction (OPC) may be employed to improve the resolution of the image that the mask forms of the substrate. In traditional resolution enhancement techniques, the optical lithographic process is simulated, and adjustments are made the mask such that the features intended by the designer are more faithfully reproduced on the substrate. Alternatively, or additionally, inverse lithographic techniques may be employed to improve the fidelity of the optical lithographic process.
Inverse lithographic techniques, like resolution enhancement techniques, seek to find a suitable mask, which when employed in a lithographic process will faithfully reproduce the intended features on the substrate. However, inverse lithography begins with the intended printed features and results in a mask. Whereas, resolution enhancement techniques begin with a mask, and iteratively make adjustments to the mask. Inverse lithography applied to microdevice manufacturing is discussed in “Solving Inverse Problems of Optical Microlithography”, Yuri Granik, Proceedings of SPIE 5754, pp. 506-526 (2004), which article is incorporated entirely herein by reference.
Another technique employed to improve the fidelity of the optical lithographic process are phase shift masks (PSM). In general, a phase shift mask capitalizes on the interference generated by phase differences inherent in the optical lithographic process to improve the resolution of the printed image. One form of phase shift masks are attenuated phase shift masks. An attenuated phase shift mask contains areas of varying light transmitting properties. For example, selected areas of the mask covered by a non-light transmitting material may be modified to allow a small amount of light to be transmitted through the area. The small amount of light transmitted through these selectively modified areas causes interference with the light traveling through the transparent areas of the mask in such a way as to improve the resolution and the process window (PW) of the printed image.
Currently, phase shift masks contain areas of low light transmission, such as 6%. Although experimentation with high light transmission masks (such as for example, 20% and 33%) has been done, background printing of unwanted features due to the higher transmission areas has always resulted. For example, high transmission masks are discussed in “High Transmission Attenuated PSM—Benefits and Limitations Through a Validation Study of 33%, 20% and 6% Transmission Masks” Nishrin Kachwala et al., Proceedings of SPIE 4000, (2000), which article is incorporated entirely herein by reference.
High transmission masks are desirable for many reasons, particularly because high transmission masks have a low mask error enhancement factor (MEEF). Mask error enhancement factor is defined as the ratio a change in the mask, for example by moving an edge, will result in a change in the printed image. Accordingly, a low mask error enhancement factor is desired. Additionally, high transmission mask typically have a higher depth of focus (DPF) and a greater uniformity of the critical dimension (CD) of the actual printed wafer. Although some of the issues of background printing of unwanted features can be suppressed by application of a second “patch” layer of non-light transmitting material, such as chrome to selected areas of the mask, this requires a second patterning step in the mask design and creation process. As the second patterning step consumes design, and manufacturing resources, there is a desire to create high transmission attenuated phase shift masks using a single mask patterning step that do not allow unwanted features to be printed on the substrate.